1. Field of the Invention
The present invention relates to memory devices, in particular, semiconductor memory devices, and most particularly, scalable, power-efficient semiconductor memory devices.
2. Background of the Art
Memory structures have become integral parts of modern VLSI systems, including digital signal processing systems. Although it typically is desirable to incorporate as many memory cells as possible into a given area, memory cell density is usually constrained by other design factors such as layout efficiency, performance, power requirements, and noise sensitivity.
In view of the trends toward compact, high-performance, high-bandwidth integrated computer networks, portable computing, and mobile communications, the aforementioned constraints can impose severe limitations upon memory structure designs, which traditional memory system and subcomponent implementations may fail to obviate.
One type of basic storage element is the static random access memory (SRAM), which can retain its memory state without the need for refreshing as long as power is applied to the cell. In an SRAM device, the memory stpte II usually stored as a voltage differential within a bistable functional element, such as an inveliter loop. A SRAIVI cell is more complex than a counterpart dynamic RAM (DRAM) cell, requjng a greater number of constituent elements, preferably transistors. Accordingly, SRAM devices commonly consume more power and dissipate more heat than a DRAM of comparable memory density; thus efficient, lower-power SRAM device designs are particularly suitable for YLSI systems having need for high-density SRAM components, providing those memory components observe the often strict overall design constraints of the particular VLSI system. Furthermore, the SRAM subsystems of many VLSI systems frequently are integrated relative to particular design implementations, with specific adaptions of the SRAM subsystem limiting, or even precluding, the scalability of the SRAM subsystem design. As a result SRAM memory subsystem designs, even those considered to be xe2x80x9cscalablexe2x80x9d, often fail to meet design limitations once these memory subsystem designs are scaled-up for use in a VLSI system With need for a greater memory cell population and!or density.
There is a need for an efficient, scalable, high-performance, low-power memory structure that allows a system designer to create a SRAM memory subsystem that satisfies strict constraints for device area, power, performance, noise sensitivity, and the like. Also, there is a need for single-port memory structures having dual-port functionality. There also is a need for such single-port structures supporting redundancy.
The present invention satisfies the above needs by providing a single-port hierarchical memory structure including memory modules, which can have memory cells disposed to store data; hierarchically-coupled local and global sense amplifiers, the local sense amplifiers being coupled with the memory cells; and hierarchically-coupled local and global row decoders, the local row decoders being coupled with the memory cells; hierarchically-coupled local and global sense amplifiers, selected local sense amplifiers being the global sense amplifier of selected memory modules; hierarchically-coupled local and global row decoders, selected local row decoders being the global row decoders of selected memory modules; and a predecoding circuit coupled with selected global row decoders. The predecoding circuit is disposed to provide predecoding at a speed substantially faster than the predetermined memory access speed of the memory structure, thereby allowing access to a selected memory cell at least twice during the memory access period, thereby providing dual-port functionality.
The present invention also includes a method obtaining dual-port functionality from a single-port hierarchical memory structure. One aspect of this embodiment entails a WRITE-AFTER-READ operation without a separate PRECHARGE cycle interposed between the READ and WRITE cycles, with the entire WRITE-AFTER-READ operation being completed within one memory access cycle of the hierarchical memory structure. Where a first datum is to be retrieved from a first memory location and a second datum is to be stored in a second memory location, the method includes locally selecting the first memory location from which the first datum is to be retrieved; locally sensing the first datum (i.e., the READ operation); globally selecting the second memory location; substantially concurrently with the globally selecting, globally sensing the first datum at the first memory location; outputting the first data subsequent to the globally sensing; inputting the second datum substantially immediately subsequent to the outputting the first datum; locally selecting the second memory location; and storing the second datum (i.e., WRITE operation). Where necessary, precharging the requisite bitlines may be performed, prior to locally sensing the first datum (i.e., PRECHARGE operation). Due to the efficiencies realized by a hierarchical memory structure according to the present invention, including the elimination of a second PRECHARGE operation immediately prior to the WRITE operation, such PRECHARGE/READ/WRITE operation can be accomplished in less than a single memory access cycle of the hierarchical memory structure. Indeed, where the context of the overall hierarchical memory structure (e.g., long interconnect lines, large overall memory structure, etc.) permits, multiple PRECHARGE/READ/WRITE operations can be accomplished in less than one memory access cycle. In another embodiment of this method, a WRITE-AFTER-WRITE operation can be accomplished by interposing a PRECHARGE operation between subsequent WRITE operations. This embodiment of the inventive method herein includes globally selecting the first memory location to which the first datum is to be stored; precharging bitlines coupled with the first memory location (PRECHARGE1 operation); locally selecting the first memory location; storing the first datum (WRITE1 operation); globally selecting the second memory location to which the second datum is to be stored; substantially concurrently with the globally selecting of the second memory location, precharging bitlines coupled with the second memory location (PRECHARGE2 operation); locally selecting the second memory location; and storing the second datum (WRITE2 operation). Despite the intervening PRECHARGE2 operation, the efficiencies afforded by a hierarchical memory structure according to the present invention nevertheless permit one or more WRITE-AFTER-WRITE operations to be performed within in less than a single memory access cycle of the hierarchical memory structure. Ther present invention also satisfies the above needs by providing a single-port hierarchical memory structure having dual port functionality in which a redundant group of memory cells can be assigned to represent a designated group of memory cells constituting a logical portion of memory in the event the designated group of memory cells is in a xe2x80x9cFAULTxe2x80x9d condition.
The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the following drawings.